Binary Decoder – Construction, Types & Applications

Digital Binary Decoder – Types & Construction

What is Binary Decoder?

A digital combinational circuit used for converting “n” bits of binary number into a combination of “2­ⁿ” or less unique and separate output lines is called digital binary decoder. In simple words, Binary Decoder used to decode a Binary Codes.

There is an enable input which can enable and disable the whole circuit. Enable can be active high and active low. Active high; when enable input is high the decoder is enabled when its low the circuit is disabled. Active low; when enable input is low the decoder is enabled.

It actually converts coded information in one format to another format. In other words, the data may be decoded by decoders same like data encoded by encoders in term of reverse operation. A decoder generates min-terms. Min-terms are products of the input, which means that decoder is made up of AND gate and NOT gates.  It can be designed with NAND gate considering the output of the decoder will be invert of AND gate decoder.

The quantity of AND gates used is equal to the number of output lines (min-terms). The NOT gate is used for inverting each input lines so the quantity of NOT gates depends on input lines.

Each minterm is associated with a unique set of binary inputs when that specific combination of binary input is applied to the decoder the concerned output is set to high or low depending on the gate(AND, NAND) used.

Types of Decoders

Some of the Line decoders are given below with details.

• 2-to-4 Line Binary Decoder
• 3-to-8 Line Decoder
• 4-to-16 Line Decoder

Also read: Counter and Types of Electronic Counters

2 to 4 Line Decoder

This decoder has 2 input lines and 2² = 4 output lines. The input is in binary format so there will be 4 possible combinations of input and for each of these combinations, there is a separate output line which goes high or low when these inputs are applied. There is an active high enable input which can enable and disable the whole decoder.

 

Construction of 2 to 4 Line Decoder using AND Gate

In this decoder, for a specific binary input combination, the specified output line gives “1” and all the other output lines become “0”. Schematic of 2 to 4 Line Decoder Using AND Gate is given below after truth table.

Truth Table

The truth table of 2 to 4 line decoder using AND gate is given below:

En is enable bit and A, B are input lines. D₀ – D_{3 ­}are output lines.

According to the truth table of “2 to 4 line decoder”, the expression for output is

D₀ = A̅B̅ = m­₀,      D₁ = A̅B = m_1,      D₂ = AB̅ = m_2,      D₃ = AB = m₃

To implement these expression we need two NOT gates and 4 AND gates for each Min-term as shown in the figure below.

As you can see, each of these outputs represents a min term m₀, m₁, m₂, m₃ which makes it easy to implement any Boolean function with 2 variables. En is applied to every AND gate whenever En = 0, all output lines will be 0.

Example:

Half Adder Implementation Using Decoder

Half adder Boolean function can be implemented with 2-4 line decoder.

Sum    =  A̅B + AB̅    =   ∑(m₁+m₂)

Carry  =  AB              =   m₃

Thus the 2^nd and 3^rd output of decoder will be ORed (sum) to form Sum and the 4^th output will be Carry as shown in the figure below.

Construction of 2 to 4 Line Decoder Using NAND Gates

NAND gate is invert of AND gate so using NAND gate instead of AND gate in decoder will invert the output of the decoder. For a specific combination of the input signal, a separate output line will give “0” instead of 1 and all other outputs will be “1”.

• Ripple Carry And Carry Look Ahead Adder

Truth Table

The truth table of 2-4 line decoder using NAND gate is given below. En is enable bit and A, B are input lines. D₀-D_{3 ­}are output lines.

According to the truth table the expression for output will be;

 D̅₀ = A̅B̅,               D̅₁ = A̅B,                D̅₂ = AB̅,                D̅₃ = AB

Implementation of these expression using NAND gates is shown in the figure below. 4 NAND gates and 2 NOT gates are used.

This decoder produces “0” on a separate output line, for a specific binary input combination.

3 to 8 Line Decoder

This decoder has 3 binary inputs and 8 output lines. 3 binary inputs mean there are 8 different combinations of inputs and for each combination of input, there is a separate output line to respond.

It is also known as binary to octal decoder because it converts binary format into octal number where each output line represents a number in the octal system.

• Digital Flip-Flops – SR, D, JK and T Flip Flops

3 to 8 Line Decoder using AND Gates

For a specific input combination, a single output line goes “1” and all other outputs become “0”. Schematic diagram of 3 to 8 Line Decoder using AND Gates is given below right after truth table.

Truth Table

The truth table of 3 to 8 line decoder using AND gate is given below. En is enable bit and A, B, C are input lines. D₀-D_{7 ­}are output lines.

 

According to the truth table, the output expression is:

D₀ = A̅B̅C̅         D₁ = A̅B̅C        D₂ = A̅BC̅       D₃ = A̅BC

D₄ = AB̅C̅         D₅ = AB̅C        D₆ = ABC̅       D₇ = ABC

These expressions can be implemented using 8 AND gates and 4 NOT gates as shown in the figure below.

Each output represents a min-term and therefore it can be used to implement any Boolean function of 3 variables.

3 to 8 Line Decoder Using 2 to 4 Line Decoder

3 to 8 line decoder can be made with two 2 to 4 line decoder with enable inputs as shown in the figure below.

Enable En will be taken as the Input MSB, when En = 0, the upper decoder will be enabled and output D₀-D₃ will be generated based on the combination of input A, B. And when En = 1, then the lower decoder will turn on and output D₄-D₇ will be generated based on input A, B.

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Implementation of Full Adder

A full adder can be implemented with a 3 to 8 line decoder. Full adder has 3 inputs C_in,A,B and 2 output Sum and Carry. The SOP expression for sum and carry is

Sum     =         C̅_in A̅B + C̅_in AB̅ + C_in A̅B̅ + C_in AB       =        ∑( m₁ + m₂ + m₄ + m₇ )

Carry    =         C̅_in AB + C_in A̅B + C_in AB̅ + C_in AB       =        ∑( m₃ + m₅ + m₆ + m₇ )

Thus the specified min-terms (output) of the decoder will be ORed (sum) together to form Full adder as shown in the figure below:

3 to 8 Line Decoder using NAND Gates

For a specific combination of 3-bit binary input, a single out of 8 output lines will give “0” and all other output lines will produce “1”.

Truth Table

The truth table of 3 to 8 line decoder using NAND gate is given below. E is enable bit and A, B, C are input lines. D₀-D_{7 ­}are output lines.

According to the truth table of 3 to 8 line decoder, the Boolean expression for is:

D̅₀ = A̅B̅C̅          D̅₁ = A̅B̅C          D̅₂ = A̅BC̅         D̅₃ = A̅BC

D̅₄ = AB̅C̅          D̅₅ = AB̅C          D̅₆ = ABC̅         D̅₇ = ABC

 These output expressions can be implemented using 8 NAND gates and 4 NOT gate as shown in the figure below.

Binary Decoder IC Configuration & Pinouts

This is NAND gate based IC. A single output line will give “0” on a unique binary input combination.

The inputs to the IC are C, B, A. Enable G̅L̅ is known as Latch-enable. When it goes from low to high it stores the input data and provides output corresponding to the stored input, ignoring the upcoming changes in the input data as long as G̅L̅ is high. When G̅L̅ is low then the input is not stored

The decoder will give output only and only when G̅2̅ and G1 are set LOW and HIGH respectively otherwise all output lines will be HIGH state “1”.

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74137 TTL 3 to 8 Line Decoder with Pin Configurations

Pin Configuration of IC 74137 TTL 3 to 8 line decoder.

Pin Number	Configuration
1	Input  A, LSB
2	Input B
3	Input  C, MSB
4	Active LOW Enable, G̅L̅
5	Active LOW Enable, G̅2̅
6	Active HIGH Enable G1
7	Output Y7
8	GND
9	Output Y6
10	Output  Y5
11	Output Y4
12	Output Y3
13	Output Y2
14	Output Y1
15	Output Y0
16	Vcc, power supply

Applications of Binary Decoders

Binary decoders are widely used in digital electronics systems. Some common application and uses of decoders are as follow:

• It is used as binary to decimal decoder.
• It is used as address decoder in memory systems of computer and CPU memory location identifications..
• It is also used as instruction decoder in the control unit of Central Processing unit (CPU).
• They can also be used to make half adder and full adder.
• Decoders are used in seven segment displays as well as data demultiplexing.

You may also read:

• Digital Logic NOR Gate
• Exclusive-NOR (XNOR) Digital Logic Gate
• Digital Logic OR Gate

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May 21, 2018 at 03:55AM by Department of EEE, ADBU: https://ift.tt/2AyIRVT