This article introduces a mixed logic design method that uses CNTFET technology combining the basic transmission gate logic, the pass transistor dual-value logic, and base CMOS logic. 14T and 15T configurations have been studied and analysed—14T for 2 to 4 decoder with low transistor count benefit and 15T for high performance in terms of power […]
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View more at https://www.electronicsforu.com/electronics-projects/electronics-design-guides/cntfet-reducing-transistor-count-power-requirement-ics.
Credit- EFY. Published by Department of EEE, ADBU: tinyurl.com/eee-adbu
